| Commit message (Collapse) | Author | Age | Files | Lines |
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When the circ-padding feature is enabled, we use maybenot, which does
not yet support rand 0.10. In the meantime, enabling this feature pulls
in rand 0.9. This is not ideal, but should be okay as a temporary
situation.
This also replaces the use of ReseedingRng (which was removed in 0.10)
with the reseeding_rng crate. This is somewhat less performant, but it
should be okay.
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I'm applying the clippy suggestion, even though in this case, using
`is_multiple_of()` instead of `%` is a bit questionable IMO, because the
`% 3` operation can never panic.
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This is now a reserved identifier. The automatic migration
changed it to a raw identifier (`r#gen`), but it's better to use a
different name.
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First, run
```
git grep -l "^edition =" |
xargs perl -i -pe 's/^edition *=.*/edition = "2024"/;'
```
Second, manually verify that all Cargo.toml files have changed,
and nothing else has changed.
Third, run cargo fmt again.
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1. Run cargo fix --edition
2. Selectively revert the "if let"->"match" changes.
These changes are meant to protect us from the lifetime changes
for "if let" bindings in Rust 2024.
But we're not actually relying on the old lifetime rules
anywhere, and the match syntax here is quite ugly.
3. Automatically revert `$pat:expr_2021` to `$pat:expr`.
(We don't actually want to restrict the expression syntax
that our macros accept).
Done with
`git grep -l expr_2021 | xargs perl -i -pe 's/expr_2021/expr/g;'`
4. Run cargo fmt.
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This patch tries to make some of the expressions around NUM_INSTRUCTIONS
more convenient. We can import it directly where it's needed, but most
uses are replaced by new type aliases for InstructionArray and
InstructionVec.
No change to any hashx_cachegrind iai benchmarks
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This is quite shoddy. It shouldn't be merged without some tidying up
and unit tests and so on. Also I am confused about the difference
between NUM_INSTRUCTIONS and model::REQUIRED_INSTRUCTIONS.
However:
generate_interp_1000x
Instructions: 220115418 (-1.147100%)
L1 Accesses: 278918725 (-0.936103%)
L2 Accesses: 25 (-98.46248%)
RAM Accesses: 414 (-0.956938%)
Estimated Cycles: 278933340 (-0.938920%)
generate_interp_1000x_c
Instructions: 272748034 (No change)
L1 Accesses: 349932970 (+0.000001%)
L2 Accesses: 76 (-1.298701%)
RAM Accesses: 405 (-0.491400%)
Estimated Cycles: 349947525 (-0.000021%)
generate_compiled_1000x
Instructions: 257344624 (-0.982784%)
L1 Accesses: 343007206 (-0.753942%)
L2 Accesses: 152502 (-17.12839%)
RAM Accesses: 809 (-0.369458%)
Estimated Cycles: 343798031 (-0.797384%)
generate_compiled_1000x_c
Instructions: 281855218 (No change)
L1 Accesses: 362569043 (+0.000002%)
L2 Accesses: 87 (-4.395604%)
RAM Accesses: 466 (-0.427350%)
Estimated Cycles: 362585788 (-0.000023%)
interp_u64_hash_1000x
Instructions: 13451818 (-0.100680%)
L1 Accesses: 16623452 (-0.105967%)
L2 Accesses: 28 (No change)
RAM Accesses: 392 (-1.507538%)
Estimated Cycles: 16637312 (-0.107138%)
interp_8b_hash_1000x_c
Instructions: 8618541 (No change)
L1 Accesses: 12316165 (+0.000032%)
L2 Accesses: 80 (-2.439024%)
RAM Accesses: 428 (-0.465116%)
Estimated Cycles: 12331545 (-0.000616%)
compiled_u64_hash_100000x
Instructions: 87312230 (-1.358594%)
L1 Accesses: 94397055 (-1.669415%)
L2 Accesses: 212 (-0.469484%)
RAM Accesses: 776 (-0.767263%)
Estimated Cycles: 94425275 (-1.669144%)
compiled_8b_hash_100000x_c
Instructions: 91547640 (No change)
L1 Accesses: 98838176 (+0.000009%)
L2 Accesses: 134 (-4.964539%)
RAM Accesses: 481 (-0.414079%)
Estimated Cycles: 98855681 (-0.000097%)
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This hoists a few decisions out of the innermost portions of
choose_dst_reg, by moving what we can out of dst_register_allowed.
Wallclock time benchmarks:
generate-interp improves, -6.0%
Cachegrind benchmarks:
generate_interp_1000x, -5.0% instructions, -11.6% L2 access, -6% RAM
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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I was trying to eliminate all the places where we copied a Program
(about 4100 bytes) except for the one final copy into a Box; but that
approach was proving too annoying. Even returning a Program via Result
will cause multiple unnecessary copies that don't optimize out.
This patch switches approaches, and instead allocates a Vec<Instruction>
presized to the correct capacity. This allocation is made as early as
possible and retained for the lifetime of the program if necessary.
This means we'll never avoid a heap allocation, but we can always
avoid extra copies and we don't need a separate Box for interpreted
programs.
Performance effects are subtle. Overall wallclock time doesn't change
much. Cachegrind shows some accesses moving up from RAM to L2 cache.
Using GDB to probe memcpy sizes shows that large (>1024b) memcpy are now
totally gone in the generate-interp test.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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Closer inspection of the CPU counters showed that the branching in
RegisterSet::index() was a big problem, contributing to the overall
CPU frontend stall bottleneck in program generation.
This new version is less general, and closer to the appraoch used by
the original C implementation. We store a sorted ArrayVec of in-set
registers, and most operations construct the RegisterSet only once
using a combined filter predicate.
Choosing a register from a set is now cheaper in branches, instructions,
and L1 cache space. We now very rarely manipulate an entire RegisterSet
in any way other than by selecting a register randomly. (Just for the
register R5 special case.)
Wallclock time benchmarks:
generate-interp improves, -7.0%
generate-x86_64 improves, -7.2%
Cachegrind benchmarks:
generate_interp_1000x, more total instructions run but a large
decrease in frontend cache misses. +4.6% instructions, +11% L1
accesses, -99% L2 access, -40% RAM access.
generate_compiled_100x, +4.0% instructions, +9.4% L1 access.
cache miss improvements: -57% L2 access, -25% RAM access.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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There was a special case in writer_pair_allowed for making add and
subtract equivalent. This patch changes RegisterWriter's encoding, using
per-opcode variants instead of per-format variants. The Add/Sub merge
can now happen earlier, when RegisterWriter is constructed.
Before and after RegisterWriter sizes are the same, at 8 bytes.
This patch removes many uses of Option<RegisterWriter> in favor
of using a new RegisterWriter::None default, and passes by value
rather than by reference.
Wallclock time benchmarks:
generate-interp improves, -7.5%
generate-x86_64 improves, -5.3%
Cachegrind benchmarks:
generate_interp_1000x, negligible change in total instructions,
improvement in cache footprint: -22.8% L2 accesses
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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Making a few comment tweaks suggested in review feedback.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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This refactors the random number generator used within HashX's program
generator so that it uses the rand::RngCore trait. The basic SipHash
powered u64 generator now implements RngCore, while a buffer layer
wraps this and provides u8 and u32 values as needed by the generator.
Some of this new RngCore layer is now exposed to the hashx crate's
public API. The intent is to allow external code to test, benchmark, or
fuzz the program generator by supplying its own random number stream.
Benchmarks show a small but confusing performance improvement
associated with this patch. About a 2% improvement in generation.
This could be due to the Rng changes. No change in compiled hash
execution performance. Even though this patch only touches program
generation, benchmarks show a 4% speedup in interpreted execution.
This seems most likely explained by instruction cache effects,
but I'm not sure.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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I was hoping most of the program generator would get inlined, so we can
resolve a lot of the edge cases at compile-time. This patch gets us
close to that, adding many inline attrs and rewriting RegisterSet with
explicit unrolling and storage types that are easier for the optimizer
to reason about.
From the disassembly of the program generator, it's now mostly one big
function with a jump table. From callgrind instruction profiles, there
are no longer obvious hotspots in register set scanning loops. It also
looks like we're often keeping per-register schedule information all
loaded into machine registers now.
Keeping the Rng entry points non-inlined for now seems to be slightly
better, by a percent or two.
There's some work left to do in compiled programs, and maybe room for
improvement in the Program representation too. That will be in a future
patch.
Benchmark shows about 20% improvement on my machine,
generate-interp time: [75.440 µs 75.551 µs 75.684 µs]
change: [-24.083% -23.775% -23.483%] (p = 0.00 < 0.05)
Performance has improved.
Found 11 outliers among 100 measurements (11.00%)
5 (5.00%) high mild
6 (6.00%) high severe
generate-x86_64 time: [96.068 µs 96.273 µs 96.540 µs]
change: [-18.699% -18.381% -18.013%] (p = 0.00 < 0.05)
Performance has improved.
Found 10 outliers among 100 measurements (10.00%)
4 (4.00%) high mild
6 (6.00%) high severe
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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This is a new pure Rust implementation of the HashX algorithm
designed by tevador for Tor's onion service proof of work puzzle v1.
HashX is a lightweight family of randomly generated hash functions.
A seed, via blake2 and siphash, drives a program generation model
which randomly selects opcodes and registers while following some
constraints that avoid timing stalls or insufficient hash mixing.
The execution of these hash funcions can be done using a pure Rust
interpreter, or about 20x faster using a very simple just in time
compiler based on the dynasm assembler crate. This has been
implemented for x86_64 and aarch64.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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