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* Switch to FixedCapacityVec 0.1.0 from crates.ioIan Jackson2023-09-063-300/+1
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* hashx: Cleanup around Instruction and NUM_INSTRUCTIONSMicah Elizabeth Scott2023-08-256-28/+24
| | | | | | | | | This patch tries to make some of the expressions around NUM_INSTRUCTIONS more convenient. We can import it directly where it's needed, but most uses are replaced by new type aliases for InstructionArray and InstructionVec. No change to any hashx_cachegrind iai benchmarks
* hashx: Avoid memcpy in Assembler::finalize()Micah Elizabeth Scott2023-08-251-1/+7
| | | | | | | | | | | | | | | | | This is a very simple change, just passing 'self' by reference instead of value. The by-value version generates a memcpy of the entire temporary program buffer which doesn't optimize out like I expected it would. The juicy impact here is a much lower cache footprint for compilation, since we avoid having yet another temporary storage location for the program data. generate_compiled_1000x Instructions: 271682605 (-0.627292%) L1 Accesses: 341834751 (-0.813903%) L2 Accesses: 56420 (-39.48365%) RAM Accesses: 618 (-20.25806%) Estimated Cycles: 342138481 (-0.867660%)
* RustfmtIan Jackson2023-08-253-3/+3
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* RFC: hashx: Make Architecture::compile take an array refIan Jackson2023-08-254-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generate_interp_1000x Instructions: 219216169 (No change) L1 Accesses: 278017243 (-0.000441%) L2 Accesses: 1257 (+4389.286%) RAM Accesses: 415 (-0.479616%) Estimated Cycles: 278038053 (+0.001744%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932964 (No change) L2 Accesses: 76 (-1.298701%) RAM Accesses: 411 (+0.243902%) Estimated Cycles: 349947729 (+0.000009%) generate_compiled_1000x Instructions: 256896028 (+0.175731%) L1 Accesses: 342543838 (+0.131802%) L2 Accesses: 149273 (-10.34924%) RAM Accesses: 810 (-0.246305%) Estimated Cycles: 343318553 (+0.106328%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569035 (-0.000001%) L2 Accesses: 88 (+1.149425%) RAM Accesses: 473 (+0.211864%) Estimated Cycles: 362586030 (+0.000010%) interp_u64_hash_1000x Instructions: 13450926 (No change) L1 Accesses: 16622561 (+0.000024%) L2 Accesses: 28 (No change) RAM Accesses: 390 (-1.015228%) Estimated Cycles: 16636351 (-0.000817%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316160 (-0.000008%) L2 Accesses: 80 (No change) RAM Accesses: 433 (+0.231481%) Estimated Cycles: 12331715 (+0.000276%) compiled_u64_hash_100000x Instructions: 87311792 (+0.000520%) L1 Accesses: 94396598 (+0.000463%) L2 Accesses: 215 (+2.380952%) RAM Accesses: 774 (-0.641849%) Estimated Cycles: 94424763 (+0.000304%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838166 (-0.000007%) L2 Accesses: 137 (+3.007519%) RAM Accesses: 488 (+0.618557%) Estimated Cycles: 98855931 (+0.000119%)
* Run maint/add-warningIan Jackson2023-08-251-0/+1
| | | | Yet another new module concurrently with a new lint.
* hashx: FixedCapacityVec: Fix clippy lintsIan Jackson2023-08-241-4/+3
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* RustfmtIan Jackson2023-08-244-6/+12
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* hashx: FixedCapacityVec: impl Send, Sync, [Ref]UnwindSafeIan Jackson2023-08-241-0/+13
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* hashx: FixedCapacityVec: TestsIan Jackson2023-08-241-0/+105
| | | | These pass miri too.
* hashx: FixedCapacityVec: introduce push_innerIan Jackson2023-08-241-7/+21
| | | | | | To support testing. No change to iai benchmarks.
* hashx: FixedCapacityVec: use *mut T, and impl DropIan Jackson2023-08-241-24/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generate_interp_1000x Instructions: 219216169 (-0.408535%) L1 Accesses: 278018470 (-0.322766%) L2 Accesses: 28 (+12.00000%) RAM Accesses: 417 (+0.724638%) Estimated Cycles: 278033205 (-0.322706%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932964 (-0.000002%) L2 Accesses: 77 (+1.315789%) RAM Accesses: 410 (+1.234568%) Estimated Cycles: 349947699 (+0.000050%) generate_compiled_1000x Instructions: 256445375 (-0.349434%) L1 Accesses: 342092951 (-0.266541%) L2 Accesses: 166505 (+9.182175%) RAM Accesses: 812 (+0.370828%) Estimated Cycles: 342953896 (-0.245532%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569037 (-0.000002%) L2 Accesses: 87 (No change) RAM Accesses: 472 (+1.287554%) Estimated Cycles: 362585992 (+0.000056%) interp_u64_hash_1000x Instructions: 13450926 (-0.006631%) L1 Accesses: 16622557 (-0.005384%) L2 Accesses: 28 (No change) RAM Accesses: 394 (+0.510204%) Estimated Cycles: 16636487 (-0.004959%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316161 (-0.000032%) L2 Accesses: 80 (No change) RAM Accesses: 432 (+0.934579%) Estimated Cycles: 12331681 (+0.001103%) compiled_u64_hash_100000x Instructions: 87311338 (-0.001022%) L1 Accesses: 94396161 (-0.000947%) L2 Accesses: 210 (-0.943396%) RAM Accesses: 779 (+0.386598%) Estimated Cycles: 94424476 (-0.000846%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838173 (-0.000003%) L2 Accesses: 133 (-0.746269%) RAM Accesses: 485 (+0.831601%) Estimated Cycles: 98855813 (+0.000134%)
* hashx: FixedCapacityVec: Note some missing stuffIan Jackson2023-08-241-0/+12
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* hashx: FixedCapacityVec: DocumentationIan Jackson2023-08-241-0/+27
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* hashx: FixedCapacityVec: Replace .into_boxed_array method with TryIan Jackson2023-08-242-9/+16
| | | | | This version pushes the panic into the call site, which seems much better. No change to the iai results.
* hashx: FixedCapacityVec: Move into its own moduleIan Jackson2023-08-245-71/+80
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* RustfmtIan Jackson2023-08-233-9/+9
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* RFC: hashx: Introduce FixedCapacityVecIan Jackson2023-08-233-6/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is quite shoddy. It shouldn't be merged without some tidying up and unit tests and so on. Also I am confused about the difference between NUM_INSTRUCTIONS and model::REQUIRED_INSTRUCTIONS. However: generate_interp_1000x Instructions: 220115418 (-1.147100%) L1 Accesses: 278918725 (-0.936103%) L2 Accesses: 25 (-98.46248%) RAM Accesses: 414 (-0.956938%) Estimated Cycles: 278933340 (-0.938920%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932970 (+0.000001%) L2 Accesses: 76 (-1.298701%) RAM Accesses: 405 (-0.491400%) Estimated Cycles: 349947525 (-0.000021%) generate_compiled_1000x Instructions: 257344624 (-0.982784%) L1 Accesses: 343007206 (-0.753942%) L2 Accesses: 152502 (-17.12839%) RAM Accesses: 809 (-0.369458%) Estimated Cycles: 343798031 (-0.797384%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569043 (+0.000002%) L2 Accesses: 87 (-4.395604%) RAM Accesses: 466 (-0.427350%) Estimated Cycles: 362585788 (-0.000023%) interp_u64_hash_1000x Instructions: 13451818 (-0.100680%) L1 Accesses: 16623452 (-0.105967%) L2 Accesses: 28 (No change) RAM Accesses: 392 (-1.507538%) Estimated Cycles: 16637312 (-0.107138%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316165 (+0.000032%) L2 Accesses: 80 (-2.439024%) RAM Accesses: 428 (-0.465116%) Estimated Cycles: 12331545 (-0.000616%) compiled_u64_hash_100000x Instructions: 87312230 (-1.358594%) L1 Accesses: 94397055 (-1.669415%) L2 Accesses: 212 (-0.469484%) RAM Accesses: 776 (-0.767263%) Estimated Cycles: 94425275 (-1.669144%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838176 (+0.000009%) L2 Accesses: 134 (-4.964539%) RAM Accesses: 481 (-0.414079%) Estimated Cycles: 98855681 (-0.000097%)
* RFC: hashx: Make Program a boxed arrayIan Jackson2023-08-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generate_interp_1000x Instructions: 222669662 (-0.146601%) L1 Accesses: 281554367 (+0.069275%) L2 Accesses: 1623 (-90.13494%) RAM Accesses: 418 (No change) Estimated Cycles: 281577112 (+0.042908%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932970 (+0.000001%) L2 Accesses: 74 (No change) RAM Accesses: 407 (-0.731707%) Estimated Cycles: 349947585 (-0.000029%) generate_compiled_1000x Instructions: 259898868 (-0.124860%) L1 Accesses: 345603941 (+0.055045%) L2 Accesses: 193008 (-4.001910%) RAM Accesses: 812 (-0.490196%) Estimated Cycles: 346597401 (+0.043228%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569040 (+0.000000%) L2 Accesses: 88 (+2.325581%) RAM Accesses: 468 (-0.636943%) Estimated Cycles: 362585860 (-0.000026%) interp_u64_hash_1000x Instructions: 13465375 (-0.024687%) L1 Accesses: 16641089 (-0.028974%) L2 Accesses: 25 (+8.695652%) RAM Accesses: 398 (+0.505051%) Estimated Cycles: 16655144 (-0.028470%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316165 (+0.000016%) L2 Accesses: 78 (No change) RAM Accesses: 430 (-0.462963%) Estimated Cycles: 12331605 (-0.000551%) compiled_u64_hash_100000x Instructions: 88514787 (-0.000365%) L1 Accesses: 95999693 (+0.000196%) L2 Accesses: 208 (-0.952381%) RAM Accesses: 782 (-0.255102%) Estimated Cycles: 96028103 (+0.000112%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838171 (-0.000002%) L2 Accesses: 137 (+3.007519%) RAM Accesses: 483 (-0.412371%) Estimated Cycles: 98855761 (-0.000053%)
* hashx: Use a boxed slice for Program storageMicah Elizabeth Scott2023-08-211-3/+3
| | | | | | | | | This is a very small change that converts our Vec cheaply into a boxed slice during program generation. Program generation speed shows no changes, and there's no change when using compiled hashes, but is a surprisingly effective 10% speedup to interpreted hash execution. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Assembly buffer sizing and tidyingMicah Elizabeth Scott2023-08-213-34/+104
| | | | | | | | | | | | | | | | | I was looking for ways to optimize out the many redundant capacity checks in the Assembler. I didn't find any promising approaches, but I also saw no evidence that it was an important bottleneck. (A simple unsafe fix didn't improve any important metrics) While I was in there, I tightened up the buffer size definitions for both x86_64 and aarch64, and added assertions to test the limits we set for the size of prologue, epilogue, and single instructions. I kept some of the inlining and data type tweaks, even though benchmarks show no difference. They seem like a step in the right direction, from the disassembly at least. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: avoid surprising overhead of enum code() methodMicah Elizabeth Scott2023-08-211-3/+3
| | | | | | | | | | | This is a very simple change that avoids a surprising performance pitfall: using the code() method on an enum from another crate caused a non-inlined function call in code where we otherwise expect a high level of compiler optimization. Replacing code() with a cast to u8 avoids this function call and allows more intensive optimization at the call site. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Rearrange destination register validator for performanceMicah Elizabeth Scott2023-08-212-12/+49
| | | | | | | | | | | | | This hoists a few decisions out of the innermost portions of choose_dst_reg, by moving what we can out of dst_register_allowed. Wallclock time benchmarks: generate-interp improves, -6.0% Cachegrind benchmarks: generate_interp_1000x, -5.0% instructions, -11.6% L2 access, -6% RAM Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: New approach to avoid memcpy in ProgramMicah Elizabeth Scott2023-08-217-63/+49
| | | | | | | | | | | | | | | | | | | | | I was trying to eliminate all the places where we copied a Program (about 4100 bytes) except for the one final copy into a Box; but that approach was proving too annoying. Even returning a Program via Result will cause multiple unnecessary copies that don't optimize out. This patch switches approaches, and instead allocates a Vec<Instruction> presized to the correct capacity. This allocation is made as early as possible and retained for the lifetime of the program if necessary. This means we'll never avoid a heap allocation, but we can always avoid extra copies and we don't need a separate Box for interpreted programs. Performance effects are subtle. Overall wallclock time doesn't change much. Cachegrind shows some accesses moving up from RAM to L2 cache. Using GDB to probe memcpy sizes shows that large (>1024b) memcpy are now totally gone in the generate-interp test. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Rewrite RegisterSet again to reduce CPU frontend stallsMicah Elizabeth Scott2023-08-216-210/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Closer inspection of the CPU counters showed that the branching in RegisterSet::index() was a big problem, contributing to the overall CPU frontend stall bottleneck in program generation. This new version is less general, and closer to the appraoch used by the original C implementation. We store a sorted ArrayVec of in-set registers, and most operations construct the RegisterSet only once using a combined filter predicate. Choosing a register from a set is now cheaper in branches, instructions, and L1 cache space. We now very rarely manipulate an entire RegisterSet in any way other than by selecting a register randomly. (Just for the register R5 special case.) Wallclock time benchmarks: generate-interp improves, -7.0% generate-x86_64 improves, -7.2% Cachegrind benchmarks: generate_interp_1000x, more total instructions run but a large decrease in frontend cache misses. +4.6% instructions, +11% L1 accesses, -99% L2 access, -40% RAM access. generate_compiled_100x, +4.0% instructions, +9.4% L1 access. cache miss improvements: -57% L2 access, -25% RAM access. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: new RegisterWriter format handles more cases transparentlyMicah Elizabeth Scott2023-08-213-99/+112
| | | | | | | | | | | | | | | | | | | | | | There was a special case in writer_pair_allowed for making add and subtract equivalent. This patch changes RegisterWriter's encoding, using per-opcode variants instead of per-format variants. The Add/Sub merge can now happen earlier, when RegisterWriter is constructed. Before and after RegisterWriter sizes are the same, at 8 bytes. This patch removes many uses of Option<RegisterWriter> in favor of using a new RegisterWriter::None default, and passes by value rather than by reference. Wallclock time benchmarks: generate-interp improves, -7.5% generate-x86_64 improves, -5.3% Cachegrind benchmarks: generate_interp_1000x, negligible change in total instructions, improvement in cache footprint: -22.8% L2 accesses Signed-off-by: Micah Elizabeth Scott <[email protected]>
* Run add_warnings on all files.Nick Mathewson2023-08-041-2/+2
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* equix, hashx: Additional comment tweaksMicah Elizabeth Scott2023-07-271-1/+1
| | | | | | More review feedback. Thanks nickm! Signed-off-by: Micah Elizabeth Scott <[email protected]>
* tor-hspow, equix, hashx: Comment tweaksMicah Elizabeth Scott2023-07-2713-190/+270
| | | | | | Making a few comment tweaks suggested in review feedback. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Simplify RegisterWriterMapMicah Elizabeth Scott2023-07-271-28/+5
| | | | | | | | | | | | I originally wrote this in an overcomplicated way, to avoid frequent initialization of a RegisterWriter array. It turns out that RegisterWriter can be fairly compact, so this extra level of indirection isn't necessary or measurably helpful. This still manages to avoid declaring RegisterWriter as Copy, by using Default to initialize the array instead of an array constructor. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* tor-hspow, equix, hashx: Make all error types CloneMicah Elizabeth Scott2023-07-271-3/+11
| | | | | | | This uses an Arc to hold std::io::Error for low-level HashX runtime errors. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Simplify hash_to_bytes, only support fixed output widthMicah Elizabeth Scott2023-07-271-4/+4
| | | | | | | | | | | | In response to review feedback. The byte output is only needed for unit tests right now, since Equi-X uses u64 output exclusively. The optimization for shorter output widths can shave tiny amounts of time off hash benchmarks, but in this case it's more helpful to avoid introducing APIs that offer parameters with incomplete compile-time range checking. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: use RngCore for HashX's internal PRNGMicah Elizabeth Scott2023-07-276-302/+380
| | | | | | | | | | | | | | | | | | | | | This refactors the random number generator used within HashX's program generator so that it uses the rand::RngCore trait. The basic SipHash powered u64 generator now implements RngCore, while a buffer layer wraps this and provides u8 and u32 values as needed by the generator. Some of this new RngCore layer is now exposed to the hashx crate's public API. The intent is to allow external code to test, benchmark, or fuzz the program generator by supplying its own random number stream. Benchmarks show a small but confusing performance improvement associated with this patch. About a 2% improvement in generation. This could be due to the Rng changes. No change in compiled hash execution performance. Even though this patch only touches program generation, benchmarks show a 4% speedup in interpreted execution. This seems most likely explained by instruction cache effects, but I'm not sure. Signed-off-by: Micah Elizabeth Scott <[email protected]>
* hashx: Implement Default for RuntimeOptionMicah Elizabeth Scott2023-07-271-11/+4
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* Update equix, hashx, tor-hspow for new clippy defaultsMicah Elizabeth Scott2023-07-271-1/+1
| | | | Just running maint/add_warning after the rebase
* hashx: register set optimizations, 20% faster generatorMicah Elizabeth Scott2023-07-276-64/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was hoping most of the program generator would get inlined, so we can resolve a lot of the edge cases at compile-time. This patch gets us close to that, adding many inline attrs and rewriting RegisterSet with explicit unrolling and storage types that are easier for the optimizer to reason about. From the disassembly of the program generator, it's now mostly one big function with a jump table. From callgrind instruction profiles, there are no longer obvious hotspots in register set scanning loops. It also looks like we're often keeping per-register schedule information all loaded into machine registers now. Keeping the Rng entry points non-inlined for now seems to be slightly better, by a percent or two. There's some work left to do in compiled programs, and maybe room for improvement in the Program representation too. That will be in a future patch. Benchmark shows about 20% improvement on my machine, generate-interp time: [75.440 µs 75.551 µs 75.684 µs] change: [-24.083% -23.775% -23.483%] (p = 0.00 < 0.05) Performance has improved. Found 11 outliers among 100 measurements (11.00%) 5 (5.00%) high mild 6 (6.00%) high severe generate-x86_64 time: [96.068 µs 96.273 µs 96.540 µs] change: [-18.699% -18.381% -18.013%] (p = 0.00 < 0.05) Performance has improved. Found 10 outliers among 100 measurements (10.00%) 4 (4.00%) high mild 6 (6.00%) high severe Signed-off-by: Micah Elizabeth Scott <[email protected]>
* Reimplement HashX in RustMicah Elizabeth Scott2023-07-2712-0/+3222
This is a new pure Rust implementation of the HashX algorithm designed by tevador for Tor's onion service proof of work puzzle v1. HashX is a lightweight family of randomly generated hash functions. A seed, via blake2 and siphash, drives a program generation model which randomly selects opcodes and registers while following some constraints that avoid timing stalls or insufficient hash mixing. The execution of these hash funcions can be done using a pure Rust interpreter, or about 20x faster using a very simple just in time compiler based on the dynasm assembler crate. This has been implemented for x86_64 and aarch64. Signed-off-by: Micah Elizabeth Scott <[email protected]>
generated by cgit v1.2.3 (git 2.46.0) at 2026-08-26 22:55:04 +0000