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Contains a small code change as `bare_relocation()` was replaced with
`value_relocation()`.
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The new conversion mechanisms in dynasm 4.0 make clippy unhappy
under aarch64.
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(Starting with version 4, dynasm wants something
that implements Into<u8>.)
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Some of these lints are in macros in a way that seems to make them
impossible to avoid, or at least, I can't figure out how to avoid them.
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First, run
```
git grep -l "^edition =" |
xargs perl -i -pe 's/^edition *=.*/edition = "2024"/;'
```
Second, manually verify that all Cargo.toml files have changed,
and nothing else has changed.
Third, run cargo fmt again.
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This patch tries to make some of the expressions around NUM_INSTRUCTIONS
more convenient. We can import it directly where it's needed, but most
uses are replaced by new type aliases for InstructionArray and
InstructionVec.
No change to any hashx_cachegrind iai benchmarks
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This is a very simple change, just passing 'self' by reference instead of
value. The by-value version generates a memcpy of the entire temporary
program buffer which doesn't optimize out like I expected it would.
The juicy impact here is a much lower cache footprint for compilation,
since we avoid having yet another temporary storage location for the program
data.
generate_compiled_1000x
Instructions: 271682605 (-0.627292%)
L1 Accesses: 341834751 (-0.813903%)
L2 Accesses: 56420 (-39.48365%)
RAM Accesses: 618 (-20.25806%)
Estimated Cycles: 342138481 (-0.867660%)
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generate_interp_1000x
Instructions: 219216169 (No change)
L1 Accesses: 278017243 (-0.000441%)
L2 Accesses: 1257 (+4389.286%)
RAM Accesses: 415 (-0.479616%)
Estimated Cycles: 278038053 (+0.001744%)
generate_interp_1000x_c
Instructions: 272748034 (No change)
L1 Accesses: 349932964 (No change)
L2 Accesses: 76 (-1.298701%)
RAM Accesses: 411 (+0.243902%)
Estimated Cycles: 349947729 (+0.000009%)
generate_compiled_1000x
Instructions: 256896028 (+0.175731%)
L1 Accesses: 342543838 (+0.131802%)
L2 Accesses: 149273 (-10.34924%)
RAM Accesses: 810 (-0.246305%)
Estimated Cycles: 343318553 (+0.106328%)
generate_compiled_1000x_c
Instructions: 281855218 (No change)
L1 Accesses: 362569035 (-0.000001%)
L2 Accesses: 88 (+1.149425%)
RAM Accesses: 473 (+0.211864%)
Estimated Cycles: 362586030 (+0.000010%)
interp_u64_hash_1000x
Instructions: 13450926 (No change)
L1 Accesses: 16622561 (+0.000024%)
L2 Accesses: 28 (No change)
RAM Accesses: 390 (-1.015228%)
Estimated Cycles: 16636351 (-0.000817%)
interp_8b_hash_1000x_c
Instructions: 8618541 (No change)
L1 Accesses: 12316160 (-0.000008%)
L2 Accesses: 80 (No change)
RAM Accesses: 433 (+0.231481%)
Estimated Cycles: 12331715 (+0.000276%)
compiled_u64_hash_100000x
Instructions: 87311792 (+0.000520%)
L1 Accesses: 94396598 (+0.000463%)
L2 Accesses: 215 (+2.380952%)
RAM Accesses: 774 (-0.641849%)
Estimated Cycles: 94424763 (+0.000304%)
compiled_8b_hash_100000x_c
Instructions: 91547640 (No change)
L1 Accesses: 98838166 (-0.000007%)
L2 Accesses: 137 (+3.007519%)
RAM Accesses: 488 (+0.618557%)
Estimated Cycles: 98855931 (+0.000119%)
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I was looking for ways to optimize out the many redundant capacity
checks in the Assembler. I didn't find any promising approaches, but
I also saw no evidence that it was an important bottleneck. (A simple
unsafe fix didn't improve any important metrics)
While I was in there, I tightened up the buffer size definitions for
both x86_64 and aarch64, and added assertions to test the limits we
set for the size of prologue, epilogue, and single instructions.
I kept some of the inlining and data type tweaks, even though benchmarks
show no difference. They seem like a step in the right direction, from
the disassembly at least.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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This is a very simple change that avoids a surprising performance
pitfall: using the code() method on an enum from another crate
caused a non-inlined function call in code where we otherwise expect
a high level of compiler optimization. Replacing code() with a cast
to u8 avoids this function call and allows more intensive optimization
at the call site.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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I was trying to eliminate all the places where we copied a Program
(about 4100 bytes) except for the one final copy into a Box; but that
approach was proving too annoying. Even returning a Program via Result
will cause multiple unnecessary copies that don't optimize out.
This patch switches approaches, and instead allocates a Vec<Instruction>
presized to the correct capacity. This allocation is made as early as
possible and retained for the lifetime of the program if necessary.
This means we'll never avoid a heap allocation, but we can always
avoid extra copies and we don't need a separate Box for interpreted
programs.
Performance effects are subtle. Overall wallclock time doesn't change
much. Cachegrind shows some accesses moving up from RAM to L2 cache.
Using GDB to probe memcpy sizes shows that large (>1024b) memcpy are now
totally gone in the generate-interp test.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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Closer inspection of the CPU counters showed that the branching in
RegisterSet::index() was a big problem, contributing to the overall
CPU frontend stall bottleneck in program generation.
This new version is less general, and closer to the appraoch used by
the original C implementation. We store a sorted ArrayVec of in-set
registers, and most operations construct the RegisterSet only once
using a combined filter predicate.
Choosing a register from a set is now cheaper in branches, instructions,
and L1 cache space. We now very rarely manipulate an entire RegisterSet
in any way other than by selecting a register randomly. (Just for the
register R5 special case.)
Wallclock time benchmarks:
generate-interp improves, -7.0%
generate-x86_64 improves, -7.2%
Cachegrind benchmarks:
generate_interp_1000x, more total instructions run but a large
decrease in frontend cache misses. +4.6% instructions, +11% L1
accesses, -99% L2 access, -40% RAM access.
generate_compiled_100x, +4.0% instructions, +9.4% L1 access.
cache miss improvements: -57% L2 access, -25% RAM access.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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More review feedback. Thanks nickm!
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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Making a few comment tweaks suggested in review feedback.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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This is a new pure Rust implementation of the HashX algorithm
designed by tevador for Tor's onion service proof of work puzzle v1.
HashX is a lightweight family of randomly generated hash functions.
A seed, via blake2 and siphash, drives a program generation model
which randomly selects opcodes and registers while following some
constraints that avoid timing stalls or insufficient hash mixing.
The execution of these hash funcions can be done using a pure Rust
interpreter, or about 20x faster using a very simple just in time
compiler based on the dynasm assembler crate. This has been
implemented for x86_64 and aarch64.
Signed-off-by: Micah Elizabeth Scott <[email protected]>
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