mirrors/arti.git/crates/hashx/src/constraints.rs, branch arti-v2.4.0

Switch Cargo.toml files to edition 2024.

2025-08-07T15:28:36Z

First, run ``` git grep -l "^edition =" | xargs perl -i -pe 's/^edition *=.*/edition = "2024"/;' ``` Second, manually verify that all Cargo.toml files have changed, and nothing else has changed. Third, run cargo fmt again.

hashx: Cleanup around Instruction and NUM_INSTRUCTIONS

2023-08-25T20:14:24Z

This patch tries to make some of the expressions around NUM_INSTRUCTIONS more convenient. We can import it directly where it's needed, but most uses are replaced by new type aliases for InstructionArray and InstructionVec. No change to any hashx_cachegrind iai benchmarks

Rustfmt

2023-08-24T16:01:44Z

hashx: FixedCapacityVec: Move into its own module

2023-08-24T12:50:20Z

Rustfmt

2023-08-23T11:02:24Z

RFC: hashx: Introduce FixedCapacityVec

2023-08-23T10:59:24Z

This is quite shoddy. It shouldn't be merged without some tidying up and unit tests and so on. Also I am confused about the difference between NUM_INSTRUCTIONS and model::REQUIRED_INSTRUCTIONS. However: generate_interp_1000x Instructions: 220115418 (-1.147100%) L1 Accesses: 278918725 (-0.936103%) L2 Accesses: 25 (-98.46248%) RAM Accesses: 414 (-0.956938%) Estimated Cycles: 278933340 (-0.938920%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932970 (+0.000001%) L2 Accesses: 76 (-1.298701%) RAM Accesses: 405 (-0.491400%) Estimated Cycles: 349947525 (-0.000021%) generate_compiled_1000x Instructions: 257344624 (-0.982784%) L1 Accesses: 343007206 (-0.753942%) L2 Accesses: 152502 (-17.12839%) RAM Accesses: 809 (-0.369458%) Estimated Cycles: 343798031 (-0.797384%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569043 (+0.000002%) L2 Accesses: 87 (-4.395604%) RAM Accesses: 466 (-0.427350%) Estimated Cycles: 362585788 (-0.000023%) interp_u64_hash_1000x Instructions: 13451818 (-0.100680%) L1 Accesses: 16623452 (-0.105967%) L2 Accesses: 28 (No change) RAM Accesses: 392 (-1.507538%) Estimated Cycles: 16637312 (-0.107138%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316165 (+0.000032%) L2 Accesses: 80 (-2.439024%) RAM Accesses: 428 (-0.465116%) Estimated Cycles: 12331545 (-0.000616%) compiled_u64_hash_100000x Instructions: 87312230 (-1.358594%) L1 Accesses: 94397055 (-1.669415%) L2 Accesses: 212 (-0.469484%) RAM Accesses: 776 (-0.767263%) Estimated Cycles: 94425275 (-1.669144%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838176 (+0.000009%) L2 Accesses: 134 (-4.964539%) RAM Accesses: 481 (-0.414079%) Estimated Cycles: 98855681 (-0.000097%)

hashx: Rearrange destination register validator for performance

2023-08-21T22:27:28Z

This hoists a few decisions out of the innermost portions of choose_dst_reg, by moving what we can out of dst_register_allowed. Wallclock time benchmarks: generate-interp improves, -6.0% Cachegrind benchmarks: generate_interp_1000x, -5.0% instructions, -11.6% L2 access, -6% RAM Signed-off-by: Micah Elizabeth Scott

hashx: New approach to avoid memcpy in Program

2023-08-21T22:27:28Z

I was trying to eliminate all the places where we copied a Program (about 4100 bytes) except for the one final copy into a Box; but that approach was proving too annoying. Even returning a Program via Result will cause multiple unnecessary copies that don't optimize out. This patch switches approaches, and instead allocates a Vec presized to the correct capacity. This allocation is made as early as possible and retained for the lifetime of the program if necessary. This means we'll never avoid a heap allocation, but we can always avoid extra copies and we don't need a separate Box for interpreted programs. Performance effects are subtle. Overall wallclock time doesn't change much. Cachegrind shows some accesses moving up from RAM to L2 cache. Using GDB to probe memcpy sizes shows that large (>1024b) memcpy are now totally gone in the generate-interp test. Signed-off-by: Micah Elizabeth Scott

hashx: Rewrite RegisterSet again to reduce CPU frontend stalls

2023-08-21T22:27:28Z

Closer inspection of the CPU counters showed that the branching in RegisterSet::index() was a big problem, contributing to the overall CPU frontend stall bottleneck in program generation. This new version is less general, and closer to the appraoch used by the original C implementation. We store a sorted ArrayVec of in-set registers, and most operations construct the RegisterSet only once using a combined filter predicate. Choosing a register from a set is now cheaper in branches, instructions, and L1 cache space. We now very rarely manipulate an entire RegisterSet in any way other than by selecting a register randomly. (Just for the register R5 special case.) Wallclock time benchmarks: generate-interp improves, -7.0% generate-x86_64 improves, -7.2% Cachegrind benchmarks: generate_interp_1000x, more total instructions run but a large decrease in frontend cache misses. +4.6% instructions, +11% L1 accesses, -99% L2 access, -40% RAM access. generate_compiled_100x, +4.0% instructions, +9.4% L1 access. cache miss improvements: -57% L2 access, -25% RAM access. Signed-off-by: Micah Elizabeth Scott

hashx: new RegisterWriter format handles more cases transparently

2023-08-21T22:27:28Z

There was a special case in writer_pair_allowed for making add and subtract equivalent. This patch changes RegisterWriter's encoding, using per-opcode variants instead of per-format variants. The Add/Sub merge can now happen earlier, when RegisterWriter is constructed. Before and after RegisterWriter sizes are the same, at 8 bytes. This patch removes many uses of Option in favor of using a new RegisterWriter::None default, and passes by value rather than by reference. Wallclock time benchmarks: generate-interp improves, -7.5% generate-x86_64 improves, -5.3% Cachegrind benchmarks: generate_interp_1000x, negligible change in total instructions, improvement in cache footprint: -22.8% L2 accesses Signed-off-by: Micah Elizabeth Scott