mirrors/arti.git/crates/hashx/src/compiler/aarch64.rs, branch main

hashx: A couple of comments about register ranges

2025-10-08T14:00:07Z

hashx: Make exceptions for clippy warnings from dynasm.

2025-10-08T14:00:07Z

The new conversion mechanisms in dynasm 4.0 make clippy unhappy under aarch64.

hashx: Make RegisterId::x() return u8 on aarch64

2025-10-07T19:18:12Z

(Starting with version 4, dynasm wants something that implements Into.)

Switch Cargo.toml files to edition 2024.

2025-08-07T15:28:36Z

First, run ``` git grep -l "^edition =" | xargs perl -i -pe 's/^edition *=.*/edition = "2024"/;' ``` Second, manually verify that all Cargo.toml files have changed, and nothing else has changed. Third, run cargo fmt again.

Fix "unnecessary parentheses around assigned value" warning on aarch64.

2025-01-06T16:03:41Z

hashx: Cleanup around Instruction and NUM_INSTRUCTIONS

2023-08-25T20:14:24Z

This patch tries to make some of the expressions around NUM_INSTRUCTIONS more convenient. We can import it directly where it's needed, but most uses are replaced by new type aliases for InstructionArray and InstructionVec. No change to any hashx_cachegrind iai benchmarks

Rustfmt

2023-08-25T17:12:56Z

RFC: hashx: Make Architecture::compile take an array ref

2023-08-25T17:12:56Z

generate_interp_1000x Instructions: 219216169 (No change) L1 Accesses: 278017243 (-0.000441%) L2 Accesses: 1257 (+4389.286%) RAM Accesses: 415 (-0.479616%) Estimated Cycles: 278038053 (+0.001744%) generate_interp_1000x_c Instructions: 272748034 (No change) L1 Accesses: 349932964 (No change) L2 Accesses: 76 (-1.298701%) RAM Accesses: 411 (+0.243902%) Estimated Cycles: 349947729 (+0.000009%) generate_compiled_1000x Instructions: 256896028 (+0.175731%) L1 Accesses: 342543838 (+0.131802%) L2 Accesses: 149273 (-10.34924%) RAM Accesses: 810 (-0.246305%) Estimated Cycles: 343318553 (+0.106328%) generate_compiled_1000x_c Instructions: 281855218 (No change) L1 Accesses: 362569035 (-0.000001%) L2 Accesses: 88 (+1.149425%) RAM Accesses: 473 (+0.211864%) Estimated Cycles: 362586030 (+0.000010%) interp_u64_hash_1000x Instructions: 13450926 (No change) L1 Accesses: 16622561 (+0.000024%) L2 Accesses: 28 (No change) RAM Accesses: 390 (-1.015228%) Estimated Cycles: 16636351 (-0.000817%) interp_8b_hash_1000x_c Instructions: 8618541 (No change) L1 Accesses: 12316160 (-0.000008%) L2 Accesses: 80 (No change) RAM Accesses: 433 (+0.231481%) Estimated Cycles: 12331715 (+0.000276%) compiled_u64_hash_100000x Instructions: 87311792 (+0.000520%) L1 Accesses: 94396598 (+0.000463%) L2 Accesses: 215 (+2.380952%) RAM Accesses: 774 (-0.641849%) Estimated Cycles: 94424763 (+0.000304%) compiled_8b_hash_100000x_c Instructions: 91547640 (No change) L1 Accesses: 98838166 (-0.000007%) L2 Accesses: 137 (+3.007519%) RAM Accesses: 488 (+0.618557%) Estimated Cycles: 98855931 (+0.000119%)

hashx: Assembly buffer sizing and tidying

2023-08-21T22:27:28Z

I was looking for ways to optimize out the many redundant capacity checks in the Assembler. I didn't find any promising approaches, but I also saw no evidence that it was an important bottleneck. (A simple unsafe fix didn't improve any important metrics) While I was in there, I tightened up the buffer size definitions for both x86_64 and aarch64, and added assertions to test the limits we set for the size of prologue, epilogue, and single instructions. I kept some of the inlining and data type tweaks, even though benchmarks show no difference. They seem like a step in the right direction, from the disassembly at least. Signed-off-by: Micah Elizabeth Scott

hashx: New approach to avoid memcpy in Program

2023-08-21T22:27:28Z

I was trying to eliminate all the places where we copied a Program (about 4100 bytes) except for the one final copy into a Box; but that approach was proving too annoying. Even returning a Program via Result will cause multiple unnecessary copies that don't optimize out. This patch switches approaches, and instead allocates a Vec presized to the correct capacity. This allocation is made as early as possible and retained for the lifetime of the program if necessary. This means we'll never avoid a heap allocation, but we can always avoid extra copies and we don't need a separate Box for interpreted programs. Performance effects are subtle. Overall wallclock time doesn't change much. Cachegrind shows some accesses moving up from RAM to L2 cache. Using GDB to probe memcpy sizes shows that large (>1024b) memcpy are now totally gone in the generate-interp test. Signed-off-by: Micah Elizabeth Scott